Thèse soutenue

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Auteur / Autrice : Hussein Adel
Direction : Habib Mehrez
Type : Thèse de doctorat
Discipline(s) : Informatique
Date : Soutenance en 2013
Etablissement(s) : Paris 6

Résumé

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High resolution wideband Analog-to-Digital Converters (ADCs) in communication systems are becoming an industrial target to provide consumers with high definition and high data rate services with high degree of flexibility. Technology advances enable high speed operation on the expense of a reduced analog resolution. To benefit from technology scaling and the accompanying digital enhancements, digital calibration can be used to leverage the analog resolution at high speed, and at lower area and power consumption. In this research, a study of the analog circuit limitations in pipeline ADCs and the possible digital calibration techniques are investigated. A foreground digital calibration technique has been applied on an 11-bit ADC prototype and measurement results prove the efficiency of digital calibration in restoring the linearity of the ADC. Design considerations for digitally calibrated ADCs are then presented and validated by system and circuit simulations to enable efficient mix between analog and digital for a highly robust digital calibration. A fast split background calibration is proposed and validated by system level simulations for pipeline ADCs. The proposed calibration technique is based on a fully deterministic approach to detect and correct the circuit errors, and thus it enables high accuracy with minimum calibration time reported in literature for a background technique. This technique is further extended for a fully deterministic split multi-stage calibration in pipeline ADCs. A circuit technique is proposed to eliminate the front-end sample and hold amplifier without sacrificing the accuracy of split ADC calibration at high frequencies.