Thèse soutenue

Une approche de coloriage d’arrêtes pour la conception d’architectures parallèles d’entrelaceurs matériels
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Auteur / Autrice : Awais Hussain Sani
Direction : Éric MartinPhilippe Coussy
Type : Thèse de doctorat
Discipline(s) : Sciences de l'ingénieur. Électronique et informatique industrielle
Date : Soutenance en 2012
Etablissement(s) : Lorient
Ecole(s) doctorale(s) : École doctorale Santé, information-communication et mathématiques, matière (Brest, Finistère)
Partenaire(s) de recherche : autre partenaire : Université européenne de Bretagne (2007-2016)

Mots clés

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Résumé

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Turbo and LDPC due to their excellent error correction capabilities are part of current telecommunication standards. However, implementation of these codes introduces new challenges mainly due to support the high data rate applications. For high data rate applications, the main memory is partitioned into smaller memory banks and multiple data values are accessed in parallel through memory to acquire required throughput. However, scrambling of data (also called interleaving) coming from TC and LDPC standards results in Memory Conflict Problem that increases the cost and latency of the system. In this thesis, different methods have been explored to allocate data in different memory banks so that different processing elements can access them concurrently without any conflict. All these methods are based on graph theory and can be divided into two steps. In first step, mapping problem is modeled as bipartite or tripartite graph respecting the data access order. Then, different algorithms are proposed to map the data into different memory banks thanks to polynomial time edge coloring algorithms. Several experiments have been performed using a set of tools developed during this thesis. This tool first finds conflict free memory mapping and then generates VHDL files that can be synthesized to design complete architecture i. E. Network, memory banks and associated controllers. These experiments have been performed.