The diminution of the critical dimensions in the semiconductor industry and the introduction of new brittle dielectric materials raise questions on the mechanical resistance of the die and the pad architectures. Nowadays, pad structures are prone to crack. More precisely, the electrical wafer sort (EWS), which allows checking the electrical functionality of the die, and the assemblies such as the wire bonding to achieve the electrical connections with the packaging, are performed at the wafer level and introduce high levels of local mechanical stresses. Indeed, during these operations, failures in the oxide layers of the interconnections are observed. Experimental techniques (e.g. profilometry, FIB/SEM) are developed after EWS and bonding with gold and copper wires to gain insight on the root causes and localization of the failures. Some designs of experiments are set up to evaluate the influence of the test and process parameters and also of the various pad designs on the mechanical robustness of the structures. In addition, a novel analysis procedure, based on nanoindentation technique, is employed to compare various pads, which are complex multilayer systems. Moreover, several finite element models, using both explicit and implicit schemes are developed to mimic the EWS test. Indeed, these models have shown their ability to reproduce the loading conditions, the contact between the testing needle tip and the pad, and some inertial effect during the test. Finally, a comprehensive set of tools to evaluate and optimize the pad architectures is presented. Guidelines for pad layouts are also given, providing integration insights in the frame of the technology development.