Projet de thèse en Informatique
Sous la direction de Fabrice Monteiro.
Thèses en préparation à l'Université de Lorraine , dans le cadre de IAEM - Ecole Doctorale Informatique, Automatique, Électronique - Électrotechnique, Mathématiques depuis le 05-11-2010 .
Error correcting codes (ECC) are since long being used to protect the data from the corruption induced by the transmission disturbances. In this context LDPC codes are currently the most promising coding technique to achieve the Shannon capacities, making them very popular in modern telecommunication applications. Despite the attractively stemming from their effectiveness, encoding and decoding LDPC codes is a rather complex task, due to the size and structure of the codes, especially when considering the ever increasing need for higher throughput in communication networks. All these constraints are setting the demand for new encoding/decoding architectures very high. In this paper, we propose effective encoder and decoder architectures for the Quasi-Cycle subclass of LDPC codes. The main features being targeted are pre-synthesis configurability and high throughput. QC-LDPC codes exhibit a highly regular structure in their parity check matrices making easier the design process to obtain the high levels of architectural parallelism necessary to achieve the required high throughputs. In order to validate our design, several encoder and decoder were implemented on FPGAs of the Altera Stratix III and Xilinx Virtex4 using different code parameters (block length and code rate) for QC-LPDC codes from the WiMAX (IEEE 802.16e) and the WiFi (IEEE 802.11n) protocols.
Digital architecture for processing the error correction Codes (LDPC)
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