Low dimensional semiconductor nanostructures, such as nanowires (NWs), have become the focus of intensive research for exploring new emergent phenomena at the nanoscale and probing their possible use in future electronics. Among these semiconductor NWs, Silicon Carbide (SiC) has very unique properties, such as wide bandgap, excellent thermal conductivity, chemical and physical stability, high electron mobility and biocompatibility. These factors makes SiC a long standing candidate material to replace silicon in specific electronic device applications operating in extreme conditions or/and harsh environments. SiC nanostructures have been studied extensively and intensively over the last decade not only for their fabrication and characterization, but also for their diverse applications. I have outlined the growth of SiC nanostructures based on different growth methods, a noteworthy feature of their characteristic properties and potential applications in the chapter one. As-grown SiC NWs fabricated by bottom-up method present a high density of structural defects, such as stacking faults. This kind of defect is one of the factors which lead to poor electrical performance (such as weak gate effect and low mobility) of the related devices. Therefore, it is required to develop a high quality of SiC nanostructures with low density of the structural defects using an alternative method, such as top-down process. Main objectives of this thesis are divided into three main parts. The first part of the thesis (Chapter two), we present the simulation results of the electrical transport and thermoelectric properties of SiC NWs. I have investigated the thermoelectric enhancement by studying the complex interplay of the size of NWs, temperature and surface roughness. Our simulation results show that the ZT of C terminated SiC NW (2.05×2.05 nm2) reaches a maximum value of 1.04 at 600K. The second part of the thesis (Chapter there) is devoted to the fabrication of high quality SiC nanostructures with controlled doping level. I have developed a top-down fabrication technique for high quality nanometer scale SiC nanopillars (NPs) using inductively coupled plasma etching. The etching behavior of SiC NPs has also been studied depending on polytypes and crystallographic orientations. Under the optimal etching conditions using a large circular mask pattern with 370 nm diameter, the obtained 4H-SiC nanopillars exhibit high anisotropy features (6.4) with a large etch depth (>7μm). A hexagonal, rhombus and triangle based pillar structures have been obtained using α-SiC (0001), 3C-SiC (001) and 3C-SiC (111) substrates, respectively. The last part of the thesis (Chapter four) is dedicated to the design and the electrical characterization of SiC nanodevices. To investigate the electrical properties of SiC nanostructures, two different kinds of SiC nanoFETs (SiC NWFET and SiC NPFET) have been fabricated by using SiC NWs and SiC NPs prepared via bottom-up method and top-down methods, respectively. In case of SiC NWFET, low resistivity ohmic contacts (378 kΩ) have been obtained after the annealing at 650 °C. Ni silicide intrusion into the SiC NW channel has been observed the annealing at 700 °C. This temperature is compared to one of other group IV materials. In case of SiC NPFET, two different types of NPFET (3C-SiC (001) and 4H-SiC (0001)) have been fabricated using our SiC nanopillars, obtained by top-down approach. The estimated values of the field-effect carrier mobility are 232.7 cm2⋅V-1s-1 for 3C-SiC (001) NPFET (#2) and 53.6 cm2⋅V-1s-1 for 4H-SiC (0001) NPFET, which is higher than the best values reported in the literature (15.9 cm2⋅V-1s-1).