Thèse de doctorat en Dispositifs de l'électronique intégrée
Sous la direction de Francis Calmon.
Soutenue en 2010
à Lyon, INSA .
Pas de résumé disponible.
Contribution to the Modeling and Characterization of Single Electron Devices
We began our work with the modelling of single electron transistor – SET. First, based on the orthodox theory, an ideal SET model implemented in Cadence framework is developed. The principle of our realistic SET model is that we use these calculated resistance values (bias dependant) in the orthodox theory (ideal model) to obtain accurate tunnel current. At the same time, we also calculate the thermionic current passing through each junction. The sum of tunnel and thermionic currents is the final current in our realistic SET model. In SET-based circuits, we have studied the impact of different CMOS technology nodes on the performance of such hybrid circuits (e. G. Detailed study on Voltage-Controlled Oscillator – VCO). To benefit from the SET advantages, we turned to the research of single electron memory – SEM (which is basically a set structure with an extra island as the memory point). We have developed the model about the charge trapped on the floating memory point of the SEM cell. We pointed out the main approach utilized in our models to calculate electron tunnel and analysed the characteristics of the charge writing and retention in the SEM. Static and dynamic models of SEM have been developed. We discussed about the modelling approaches especially the algorithms of each model. Static model is used to get the final electron number in the floating island of SEM, while dynamic model allows estimating the charge variation with time function of voltage biasing and finally extracting the writing and retention times. These two models can complement each other and some preliminary results were shown. Finally, the process of room temperature SET developed in the University of Sherbrooke is presented. We presented the main problems in the fabrication. We finished this last chapter with the proposal of a possible process to fabricate single electron memories