Thèse de doctorat en Micro et nano-électronique
Sous la direction de Abdelkader Souifi.
Soutenue en 2009
à Lyon, INSA .
Silicon feature length scaling has been shrinking exponentially since the early 1970’s to improve the performance, integration density and the price of the electronic integrated circuits. However, the conventional transistor on bulk shows its limits in term of miniaturization. To further improve the trade-off between the power dissipation and the gate switch delay of the integrated circuits, several avenues are pursuing : new materials and new transistors structures. The multiple gate architecture is one of the most promising solutions to extend CMOS down to the 22 nm node and beyond. In this context, this work concerns the study, the fabrication and the electrical properties of 3D Multiple Channel CMOS transistors (MCFET). Thanks to their 3D GAA configuration, it is shown that such architectures can meet both the high performance and low power consumption requirements. However, our in-depth electrical characterization and the development of an analytical model, highlight several parameters to cause a deterioration of the MCFET performance. In particular, the series resistances and the parasitic side capacitances are pointed out as the major players of this degradation. Numerical simulations are then used to minimize those two components and maximize the static and dynamic performance of such archietctures. These optimizations are then implemented on silicon thanks to innovation integrations (including internal spacers). Transistors characteristics of the optimized transistors are analysed and discussed down to 50 nm gate length. The performance is compared directly to the high performance and low power consumption state of the art. Finally, a propective study is carried out to-integrate N+ like and P+ like materials in CMCFET architectures for applications necessitating low threshold voltages (RF and low voltage applications)
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